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FEATURES ADF4216: 550 MHz/1.2 GHz ADF4217: 550 MHz/2.0 GHz ADF4218: 550 MHz/2.5 GHz 2.7 V to 5.5 V Power Supply Selectable Charge Pump Currents Selectable Dual Modulus Prescaler IF: 8/9 or 16/17 RF: 32/33 or 64/65 3-Wire Serial Interface Power-Down Mode
Dual RF PLL Frequency Synthesizers ADF4216/ADF4217/ADF4218
GENERAL DESCRIPTION
APPLICATIONS Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA) Base Stations for Wireless Radio (GSM, PCS, DCS, CDMA, WCDMA) Wireless LANS Communications Test Equipment CATV Equipment
The ADF4216/ADF4217/ADF4218 are dual frequency synthesizers that can be used to implement local oscillators (LOs) in the upconversion and downconversion sections of wireless receivers and transmitters. They can provide the LO for both the RF and IF sections. They consist of a low-noise digital PFD (Phase Frequency Detector), a precision charge pump, a programmable reference divider, programmable A and B counters, and a dual-modulus prescaler (P/P+1). The A (6-bit) and B (11-bit) counters, in conjunction with the dual modulus prescaler (P/P+1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter), allows selectable REFIN frequencies at the PFD input. A complete PLL (PhaseLocked Loop) can be implemented if the synthesizers are used with an external loop filter and VCOs (Voltage Controlled Oscillators). Control of all the on-chip registers is via a simple 3-wire interface. The devices operate with a power supply ranging from 2.7 V to 5.5 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2 VP1 VP2
N = BP + A 11-BIT IF B-COUNTER IFINA IFINB IF PRESCALER 6-BIT IF A-COUNTER
ADF4216/ADF4217/ADF4218
PHASE COMPARATOR CHARGE PUMP IF LOCK DETECT CPIF
REFIN
OSCILLATOR 14-BIT IF R-COUNTER OUTPUT MUX 22-BIT DATA REGISTER SDOUT MUXOUT
CLOCK DATA LE
14-BIT IF R-COUNTER N = BP + A 11-BIT RF B-COUNTER RFINA RFINB RF PRESCALER 6-BIT RF A-COUNTER
RF LOCK DETECT
CHARGE PUMP PHASE COMPARATOR
CPRF
DGNDRF
AGNDRF
DGNDIF
DGNDIF
AGNDIF
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2000
1 (V 1 = V 2 = ADF4216/ADF4217/ADF4218-SPECIFICATIONSotherwise noted.) 3 V V 1, V 2 V 1, V 2 6.0 V ; AGND = DGND = AGND = DGND = 0 V; T = T to T unless
DD DD DD DD P P RF RF IF IF A MIN MAX
10%, 5 V
10%;
Parameter
RF/IF CHARACTERISTICS (3 V) RF Input Frequency (RFIN) ADF4216 ADF4217 ADF4218 IF Input Frequency (IFIN) RF Input Sensitivity IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 RF/IF CHARACTERISTICS (5 V) RF Input Frequency (RFIN) ADF4216 ADF4217 ADF4218 IF Input Frequency (IFIN) RF Input Sensitivity IF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency5 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance Oscillator Input Current LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES VDD1 VDD2 VP
B Version
B Chips2
Unit
Test Conditions/Comments See Figure 3 for Input Circuit. For lower frequency operation (below the minimum stated) use a square wave source.
0.2/1.2 0.2/2.0 0.5/2.5 45/550 -15/+4 -10/+4 165
0.2/1.2 0.2/2.0 0.5/2.5 45/550 -15/+4 -10/+4 165
GHz min/max GHz min/max GHz min/max MHz min/max dBm min/max dBm min/max MHz max
0.2/1.2 0.2/2.0 0.5/2.5 25/550 -15/+4 -10/+4 200 5/40 0.5 10 100 40
0.2/1.2 0.2/2.0 0.5/2.5 25/550 -15/+4 -10/+4 200 5/40 0.5 10 100 40
GHz min/max GHz min/max GHz min/max MHz min/max dBm min/max dBm min/max MHz max MHz min/max V p-p min pF max A max MHz max
See Figure 3 for Input Circuit. For lower frequency operation (below the minimum stated) use a square wave source.
For f < 5 MHz, use dc-coupled square wave (0 to VDD). AC-Coupled. When DC-Coupled: 0 to VDD max (CMOS-Compatible)
4.5 1.125 1 1 1 10 10 0.8 x VDD 0.2 x VDD 1 10 100 VDD - 0.4 0.4 2.7/5.5 VDD1 VDD1/6.0
4.5 1.125 1 1 1 10 10 0.8 x VDD 0.2 x VDD 1 10 100 VDD - 0.4 0.4 2.7/5.5 VDD1 VDD1/6.0
mA typ mA typ % typ nA typ % typ % max % typ V min V max A max pF max A max V min V max V min/V max V min/V max
0.5 V VCP VCP = VP /2
VP - 0.5 V
IOH = 500 A IOL = 500 A
AVDD
VP
6.0 V
-2-
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ADF4216/ADF4217/ADF4218
Parameter POWER SUPPLIES (Continued) IDD (RF + IF)6 ADF4216 ADF4217 ADF4218 IDD (RF Only) ADF4216 ADF4217 ADF4218 IDD (IF Only) ADF4216 ADF4217 ADF4218 IP (IP1 + IP2) Low-Power Sleep Mode NOISE CHARACTERISTICS Phase Noise Floor7 Phase Noise Performance8 ADF4216, ADF4217, ADF4218 (IF)9 ADF4216 (RF): 900 MHz Output10 ADF4217 (RF): 900 MHz Output10 ADF4218 (RF): 900 MHz Output10 ADF4216 (RF): 836 MHz Output11 ADF4217 (RF): 1750 MHz Output12 ADF4217 (RF): 1750 MHz Output13 ADF4218 (RF): 1960 MHz Output14 Spurious Signals ADF4216 ADF4217, ADF4218 (IF)9 ADF4216 (RF): 900 MHz Output10 ADF4217 (RF): 900 MHz Output10 ADF4218 (RF): 900 MHz Output10 ADF4216 (RF): 836 MHz Output11 ADF4217 (RF): 1750 MHz Output12 ADF4217 (RF): 1750 MHz Output13 ADF4218 (RF): 1960 MHz Output14 B Version B Chips2 Unit Test Conditions/Comments See TPC 22 and TPC 23 9.0 mA typical at VDD = 3 V and TA = 25C 12 mA typical at VDD = 3 V and TA = 25C 14 mA typical at VDD = 3 V and TA = 25C 5.0 mA typical at VDD = 3 V and TA = 25C 7.0 mA typical at VDD = 3 V and TA = 25C 9.0 mA typical at VDD = 3 V and TA = 25C 4.5 mA typical at VDD = 3 V and TA = 25C 4.5 mA typical at VDD = 3 V and TA = 25C 4.5 mA typical at VDD = 3 V and TA = 25C TA = 25C 0.5 A typical @ 25 kHz PFD Frequency @ 200 kHz PFD Frequency @ VCO Output @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 300 Hz Offset and 30 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 200 Hz Offset and 10 kHz PFD Frequency @ 1 kHz Offset and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 30 kHz/60 kHz and 30 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency @ 10 kHz/20 kHz and 10 kHz PFD Frequency @ 200 kHz/400 kHz and 200 kHz PFD Frequency
18 21 25 10 14 18 9 9 9 0.6 5 -171 -164 -91 -87 -88 -90 -78 -85 -66 -84 -97/-106 -98/-106 -91/-100 -80/-84 -80/-84 -88/-90 -65/-73 -80/-84
9 12 14 5 7 9 4.5 4.5 4.5 0.6 5 -171 -164 -91 -87 -88 -90 -78 -85 -66 -84 -97/-106 -98/-106 -91/-100 -80/-84 -80/-84 -88/-90 -65/-73 -80/-84
mA max mA max mA max mA max mA max mA max mA max mA max mA max mA max A max dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ dB typ
NOTES 1 Operating temperature range is as follows: B Version: -40C to +85C. 2 The B Chip specifications are given as typical values. 3 This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the IF/RF input is divided down to a frequency that is less than this value. 4 VDD1 = VDD2 = 3 V; For VDD1 = VDD2 = 5 V, use CMOS-compatible levels. 5 Guaranteed by design. Sample tested to ensure compliance. 6 P = 16; RFIN = 900 MHz; IFIN = 540 MHz. 7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 8 The phase noise is measured with the EVAL-ADF421XEB1 Evaluation Board and the HP8562E Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (f REFOUT = 10 MHz @ 0 dBm). 9 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fIF = 540 MHz; N = 2700; Loop B/W = 20 kHz. 10 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 11 fREFIN = 10 MHz; fPFD = 30 kHz; Offset frequency = 300 Hz; fRF = 836 MHz; N = 27867; Loop B/W = 3 kHz. 12 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1750 MHz; N = 8750; Loop B/W = 20 kHz. 13 fREFIN = 10 MHz; fPFD = 10 kHz; Offset frequency = 200 Hz; fRF = 1750 MHz; N = 175000; Loop B/W = 1 kHz. 14 fREFIN = 10 MHz; fPFD = 200 kHz; Offset frequency = 1 kHz; fRF = 1960 MHz; N = 9800; Loop B/W = 20 kHz. Specifications subject to change without notice.
REV. 0
-3-
ADF4216/ADF4217/ADF4218 TIMING CHARACTERISTICS
Parameter t1 t2 t3 t4 t5 t6 Limit at TMIN to TMAX (B Version) 10 10 25 25 10 20
(VDD1 = VDD2 = 3 V 10%, 5 V 10%; VP1, VP2 = VDD , 5 V TA = TMIN to TMAX unless otherwise noted.)
10%; AGND = DGND = 0 V;
Unit ns min ns min ns min ns min ns min ns min
Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth
NOTES Guaranteed by design but not production tested. Specification subject to change without notice.
t3
CLOCK
t4
t1
DATA DB21 (MSB) DB20
t2
DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1)
t6
LE LE
t5
Figure 1. Timing Diagram
ABSOLUTE MAXIMUM RATINGS 1, 2
(TA = 25C unless otherwise noted)
VDD1 to GND3 . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD1 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V VP1, VP2 to GND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VP1, VP2 to VDD1 . . . . . . . . . . . . . . . . . . . . -0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . -0.3 V to VP + 0.3 V REFIN, RFINA, RFINB, IFINA, IFINB to GND . . . . . . . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . 150C TSSOP JA Thermal Impedance . . . . . . . . . . . . . 150.4C/W
Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high-performance RF integrated circuit with an ESD rating of < 2 kV and it is ESD sensitive. Proper precautions should be taken for handling and assembly. 3 GND = AGND = DGND = 0 V.
TRANSISTOR COUNT
11749 (CMOS) and 522 (Bipolar).
ORDERING GUIDE
Model ADF4216BRU ADF4217BRU ADF4218BRU
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP) Thin Shrink Small Outline Package (TSSOP)
Package Option* RU-20 RU-20 RU-20
*Contact the factory for chip availability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADF4216/ADF4217/ADF4218 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
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ADF4216/ADF4217/ADF4218
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic 1 VDD1
Function Positive Power Supply for the RF Section. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD1 should have a value of between 2.7 V and 5.5 V. VDD1 must have the same potential as VDD2. Power Supply for the RF Charge Pump. This should be greater than or equal to VDD. Output from the RF Charge Pump. When enabled this provides ICP to the external loop filter, which in turn drives the external VCO. Ground Pin for the RF Digital Circuitry. Input to the RF Prescaler. This low-level input signal is normally ac-coupled to the external VCO. Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Ground Pin for the RF Analog Circuitry. Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 k. This input can be driven from a TTL or CMOS crystal oscillator or it can be ac-coupled. Ground Pin for the IF Digital (Interface and Control Circuitry). This multiplexer output allows either the IF/RF lock detect, the scaled RF, or the scaled Reference Frequency to be accessed externally. See Table V. Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the 22-bit shift register on the CLK rising edge. This input is a high impedance CMOS input. Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This input is a high impedance CMOS input. Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into one of the four latches, the latch being selected using the control bits. Ground Pin for the IF Analog Circuitry. Complementary Input to the IF Prescaler. This point should be decoupled to the ground plane with a small bypass capacitor, typically 100 pF. Input to the IF Prescaler. This low-level input signal is normally ac-coupled to the external VCO. Ground Pin for the IF Digital, Interface, and Control Circuitry. Output from the IF Charge Pump. When enabled this provides ICP to the external loop filter, which in turn drives the external VCO. Power Supply for the IF Charge Pump. This should be greater than or equal to VDD. Positive Power Supply for the IF, Interface, and Oscillator Sections. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. VDD2 should have a value of between 2.7 V and 5.5 V. VDD2 must have the same potential as VDD1.
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
V P1 CPRF DGNDRF RFINA RFINB AGNDRF REFIN DGNDIF MUXOUT CLK DATA LE AGNDIF IFINB IFINA DGNDIF CPIF V P2 VDD2
PIN CONFIGURATION
VDD1 1 VP1 2 CPRF
3
20 19 18
VDD2 VP2 CPIF DGNDIF IFINA IFINB AGNDIF LE DATA CLK
DGNDRF 4 RFINA 5 RFINB 6 AGNDRF 7 REFIN 8 DGNDIF MUXOUT
9 10
TSSOP
17 16
ADF4216/ ADF4217/ ADF4218
15 14 13 12 11
REV. 0
-5-
ADF4216/ADF4217/ADF4218 -Typical Performance Characteristics
0
FREQ-UNIT PARAM-TYPE DATA-FORMAT KEYWORD GHz S MA R IMPEDANCE - OHMS 50
-10 -20
OUTPUT POWER - dB
REFERENCE LEVEL = -4.2dBm
VDD = 3V, VP = 5V ICP = 4.375mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 30
FREQ 0.0 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85 0.95 1.05 1.15 1.25
MAGS11 0.957111193 0.963546793 0.953621785 0.953757706 0.929831379 0.908459709 0.897303634 0.876862863 0.849338092 0.858403269 0.841888714 0.840354983 0.822165839
ANGS11 -3.130429321 -6.686426265 -11.19913586 -15.35637483 -20.3793432 -22.69144845 -27.07001443 -31.32240763 -33.68058163 -38.57674885 -41.48606772 -45.97597958 -49.19163116
FREQ 1.35 1.45 1.55 1.65 1.75 1.85 1.95 2.05 2.15 2.25 2.35 2.45 2.55
MAGS11 0.816886959 0.825983016 0.791737125 0.770543186 0.793897072 0.745765233 0.7517547 0.745594889 0.713387801 0.711578577 0.698487131 0.669871818 0.668353367
ANGS11 -51.80711782 -56.20373378 -61.21554647 -61.88187496 -65.39516615 -69.24884474 -71.21608147 -75.93169947 -78.8391674 -81.71934806 -85.49067481 -88.41958754 -91.70921678
-30 -40 -50 -60 -70 -80 -90
-90dBc
-100 -400kHz -200kHz 900MHz +200kHz +400kHz
TPC 1. S-Parameter Data for the AD4218 RF Input (Up to 2.5 GHz)
TPC 4. ADF4218 RF Reference Spurs (900 MHz, 200 kHz, 20 kHz)
0 -5 VDD = 3.3V VP = 3.3V
10dB/DIVISION -40 -50 -60
RL = -40dBc/Hz
RMS NOISE = 0.55
RF INPUT POWER - dBm
-10 -15 TA = -40 C -20 -25 -30 -35
PHASE NOISE - dBc/Hz
0.55 rms -70 -80 -90 -100 -110 -120
TA = +85 C
TA = +25 C 0 0.5 1.5 2 1 RF INPUT FREQUENCY - GHz 2.5 3
-130 -140 100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
TPC 2. Input Sensitivity for the ADF4218 (RF)
TPC 5. ADF4218 RF Integrated Phase Noise (900 MHz, 200 kHz, 20 kHz)
0 -10 -20 OUTPUT POWER - dB -30 -40 -50 -60 -70 -80 -90 -100 -2kHz -1kHz 900MHz +1kHz +2kHz -90dBc/Hz REFERENCE LEVEL = -4.2dBm VDD = 3V, VP = 5V ICP = 4.375mA PFD FREQUENCY = 200kHz
10dB/DIVISION -40 -50 -60
RL = -40dBc/Hz
RMS NOISE = 0.65
PHASE NOISE - dBc/Hz
LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 19
0.65 rms -70 -80 -90 -100 -110 -120 -130 -140 100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
TPC 3. ADF4218 RF Phase Noise (900 MHz, 200 kHz, 20 kHz)
TPC 6. ADF4218 RF Integrated Phase Noise (900 MHz, 200 kHz, 35 kHz)
-6-
REV. 0
ADF4216/ADF4217/ADF4218
0 -10 -20
REFERENCE LEVEL = -4.2dBm
0
VDD = 3V, VP = 5V ICP = 4.375mA PFD FREQUENCY = 200kHz POWER OUTPUT - dB LOOP BANDWIDTH = 35kHz RES. BANDWIDTH = 1kHz VIDEO BANDWIDTH = 1kHz SWEEP = 2.5 SECONDS AVERAGES = 30
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100
REFERENCE LEVEL = -5.7dBm
VDD = 3V, VP = 5V ICP = 4.375mA PFD FREQUENCY = 30kHz LOOP BANDWIDTH = 3kHz RES. BANDWIDTH = 3Hz VIDEO BANDWIDTH = 3Hz SWEEP = 255 SECONDS POSITIVE PEAK DETECT MODE -78dBc/Hz
OUTPUT POWER - dB
-30 -40 -50 -60 -70 -80 -90
-89dBc
-100
-400kHz
-200kHz
900MHz
+200kHz
+400kHz
-80kHz
-40kHz
1750MHz
+40kHz
+80kHz
TPC 7. ADF4218 RF Reference Spurs (900 MHz, 200 kHz, 35 kHz)
TPC 10. ADF4218 RF Reference Spurs (1750 MHz, 30 kHz, 3 kHz)
0 -10 -20
OUTPUT POWER - dB
-120
REFERENCE LEVEL = -8.0dBm
VDD = 3V, VP = 5V ICP = 4.375mA PFD FREQUENCY = 30kHz RES. BANDWIDTH = 10kHz VIDEO BANDWIDTH = 10kHz SWEEP = 477ms AVERAGES = 10 PHASE NOISE - dBc/Hz LOOP BANDWIDTH = 3kHz
VDD = 3V VP = 5V -130
-30 -40 -50 -60 -70 -80 -90
-140
-150
-160
-74dBc/Hz
-170
-100 -400Hz -200Hz 1750MHz +200Hz +400Hz
-180
1
10 100 1000 PHASE DETECTOR FREQUENCY - kHz
10000
TPC 8. ADF4218 RF Phase Noise (1750 MHz, 30 kHz, 3 kHz)
TPC 11. ADF4218 RF Phase Noise vs. PFD Frequency
10dB/DIVISION -40 -50 -60
RL = -40dBc/Hz
RMS NOISE = 1.8
-60 VDD = 3V VP = 3V
PHASE NOISE - dBc/Hz
PHASE NOISE - dBc/Hz
-70
-70 1.8 rms -80 -90 -100 -110 -120 -130 -140 100Hz
-80
-90
FREQUENCY OFFSET FROM 1750MHz CARRIER
1MHz
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
TPC 9. ADF4218 RF Integrated Phase Noise (1750 MHz, 30 kHz, 3 kHz)
TPC 12. ADF4218 RF Phase Noise vs. Temperature (900 MHz, 200 kHz, 20 kHz)
REV. 0
-7-
ADF4216/ADF4217/ADF4218
-60 VDD = 3V VP = 5V
PHASE NOISE - dBc/Hz
10dB/DIVISION -40 -50 -60 0.60 rms -70 -80 -90 -100 -110 -120 -130 RL = -40dBc/Hz RMS NOISE = 0.52
FIRST REFERENCE SPUR - dBc
-70
-80
-90
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
-140 100Hz
FREQUENCY OFFSET FROM 900MHz CARRIER
1MHz
TPC 13. ADF4218 RF Reference Spurs vs. Temperature (900 MHz, 200 kHz, 20 kHz)
TPC 16. ADF4218 IF Integrated Phase Noise (540 MHz, 200 kHz, 20 kHz)
-5 -15
FIRST REFERENCE SPUR - dBc
0
-25 -35 -45 -55 -65 -75 -85 -95 -105 0 1 2 3 TUNING VOLTAGE - Volts
VDD = 3V VP = 5V
OUTPUT POWER - dB
-10 -20 -30 -40 -50 -60 -70 -80 -90
REFERENCE LEVEL = -4.2dBm
VDD = 3V, VP = 5V ICP = 5mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz VIDEO BANDWIDTH = 10Hz SWEEP = 2.5 SECONDS AVERAGES = 30
-88.0dBc
4
5
-100 -400kHz -200kHz 900MHz +200kHz +400kHz
TPC 14. ADF4218 RF Reference Spurs vs. VTUNE (900 MHz, 200 kHz, 20 kHz)
TPC 17. ADF4218 IF Reference Spurs (540 MHz, 200 kHz, 20 kHz)
0 -10 -20 REFERENCE LEVEL = -4.2dBm VDD = 3V, VP = 5V ICP = 4.375mA PFD FREQUENCY = 200kHz LOOP BANDWIDTH = 20kHz RES. BANDWIDTH = 10Hz -40 -50 -60 -70 -80 -90 -100 -2kHz -1kHz 900MHz +1kHz +2kHz VIDEO BANDWIDTH = 10Hz SWEEP = 1.9 SECONDS AVERAGES = 19 -89dBc/Hz
-120 VDD = 3V VP = 5V -130
PHASE NOISE - dBc/Hz
OUTPUT POWER - dB
-30
-140
-150
-160
-170
-180
1
10 100 1000 PHASE DETECTOR FREQUENCY - kHz
10000
TPC 15. ADF4218 IF Phase Noise (540 MHz, 200 kHz, 20 kHz)
TPC 18. ADF4218 IF Phase Noise vs. PFD Frequency
-8-
REV. 0
ADF4216/ADF4217/ADF4218
-60 VDD = 3V VP = 3V 3.0 VDD = 3V VP = 3V 2.5
PHASE NOISE - dBc/Hz
-70 2.0
DIDD - mA
-80
1.5
1.0 -90 0.5
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
0
0
50 100 150 PRESCALER OUTPUT FREQUENCY - MHz
200
TPC 19. ADF4218 IF Phase Noise vs. Temperature (540 MHz, 200 kHz, 20 kHz)
TPC 22. DIDD vs. Prescaler Output Frequency (ADF4218, RF Only)
-60 VDD = 3V VP = 5V -70
10 9
ADF4218
8 7
AIDD - mA
FIRST REFERENCE SPUR - dBc
6 5 4 3
ADF4217
-80
ADF4216
-90
2 1
-100 -40
-20
0
20 40 TEMPERATURE - C
60
80
100
0
32/33 PRESCALER VALUE
64/65
TPC 20. ADF4218 IF Reference Spurs vs. Temperature (540 MHz, 200 kHz, 20 kHz)
TPC 23. ADF4218 AIDD vs. Prescaler Value (RF)
-5 -15
FIRST REFERENCE SPUR - dBc
-25 -35 -45 -55 -65 -75 -85 -95 -105 0 1 2 3 TUNING VOLTAGE - Volts
VDD = 3V VP = 5V
4
5
TPC 21. ADF4218 IF Reference Spurs vs. VTUNE (900 MHz, 200 kHz, 20 kHz)
REV. 0
-9-
ADF4216/ADF4217/ADF4218
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION Pulse Swallow Function
The reference input stage is shown below in Figure 2. SW1 and SW2 are normally closed switches. SW3 is normally open. When power-down is initiated, SW3 is closed and SW1 and SW2 are opened. This ensures that there is no loading of the REFIN pin on power-down.
POWER-DOWN CONTROL
The A and B counters, in conjunction with the dual modulus prescaler make it possible to generate output frequencies which are spaced only by the Reference Frequency divided by R. The equation for the VCO frequency is as follows: fVCO = [(P x B) + A] x fREFIN/R fVCO = Output frequency of external voltage controlled oscillator (VCO). P = Preset modulus of dual modulus prescaler (8/9, 16/17, etc.). = Preset Divide Ratio of binary 11-bit counter (1 to 2047). = Preset Divide Ratio of binary 6-bit A counter (0 to 63).
NC SW2 REFIN NC
100k TO R COUNTER BUFFER
B A
SW1 SW3 NO
fREFIN = Output frequency of the external reference frequency oscillator. R = Preset divide ratio of binary 14-bit programmable reference counter (1 to 16383).
Figure 2. Reference Input Stage
IF/RF INPUT STAGE
R COUNTER
The IF/RF input stage is shown in Figure 3. It is followed by a 2-stage limiting amplifier to generate the CML clock levels needed for the prescaler.
BIAS GENERATOR 2k 2k
The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.
AVDD
N = BP+A TO PFD
11-BIT B COUNTER
RFINA
FROM IF/RF INPUT STAGE
PRESCALER P/P+1 MODULUS CONTROL
LOAD LOAD 6-BIT A COUNTER
RFINB
N DIVIDER
AGND
Figure 3. IF/RF Input Stage
PRESCALER
Figure 4. A and B Counters
PHASE FREQUENCY DETECTOR (PFD) AND CHARGE PUMP
The dual modulus prescaler (P/P+1), along with the A and B counters, enables the large division ratio, N, to be realized (N = BP + A). This prescaler, operating at CML levels, takes the clock from the IF/RF input stage and divides it down to a manageable frequency for the CMOS A and B counters. It is based on a synchronous 4/5 core. The prescaler is selectable. On the IF side it can be set to either 8/9 (DB20 of the IF AB Counter Latch set to 0) or 16/17 (DB20 set to 1). On the RF side it can be set to 64/65 (DB20 of the RF AB Counter Latch set to 0) or 32/33 (DB20 set to 1). See Tables IV and VI.
A AND B COUNTERS
The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them. Figure 5 is a simplified schematic.
HI D1 U1 IN CLR1 DELAY ELEMENT U3 CHARGE PUMP CP Q1 UP
The A and B CMOS counters combine with the dual modulus prescaler to allow a wide ranging division ratio in the PLL feedback counter. The devices are guaranteed to work when the prescaler output is 165 MHz or less. Typically they will work with 200 MHz output from the prescaler. -10-
HI
CLR2 DOWN D1 Q1 U1
- IN
Figure 5. PFD Simplified Schematic
REV. 0
ADF4216/ADF4217/ADF4218
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4216 family allows the user to access various internal points on the chip. The state of MUXOUT is controlled by P3, P4, P11 and P12. See Tables III and V. Figure 6 shows the MUXOUT section in block diagram form.
DVDO
2. The IF Counter Reset mode resets the R and N counters in the IF section and also puts the IF charge pump into threestate. The RF Counter Reset mode resets the R and N counters in the RF section and also puts the RF charge pump into three-state. The IF and RF Counter Reset mode does both of the above. Upon removal of the reset bits, the N counter resumes counting in close alignment with the R counter (maximum error is one prescaler output cycle). 3. The Fastlock mode uses MUXOUT to switch a second loop filter damping resistor to ground during Fastlock operation. Activation of Fastlock occurs whenever RF CP Gain in the RF Reference counter is set to one.
POWER-DOWN
IF ANALOG LOCK DETECT IF R COUNTER OUTPUT IF N COUNTER OUTPUT IF/RF ANALOG LOCK DETECT RF R COUNTER OUTPUT RF N COUNTER OUTPUT RF ANALOG LOCK DETECT MUX CONTROL MUXOUT
It is possible to program the ADF4216 family for either synchronous or asynchronous power-down on either the IF or RF side.
DGND
Synchronous IF Power-Down
Figure 6. MUXOUT Circuit
Lock Detect
MUXOUT can be programmed for analog lock detect. The Nchannel open-drain analog lock detect should be operated with an external pull-up resistor of 10 k nominal. When lock has been detected it is high with narrow low-going pulses.
INPUT SHIFT REGISTER
Programming a "1" to P7 of the ADF4216 family will initiate a power-down. If P2 of the ADF4216 family has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into threeState and then complete the power-down.
Asynchronous IF Power-Down
The functional block diagram for the ADF4216 family is shown on Page 1. The main blocks include a 22-bit input shift register, a 14-bit R counter and an 17-bit N counter, comprising a 6-bit A counter and an 11-bit B counter. Data is clocked into the 22bit shift register on each rising edge of CLK. The data is clocked in MSB first. Data is transferred from the shift register to one of four latches on the rising edge of LE. The destination latch is determined by the state of the two control bits (C2, C1) in the shift register. These are the two LSBs DB1, DB0 as shown in the timing diagram of Figure 1. The truth table for these bits is shown in Table I.
Table I. C2, C1 Truth Table
If P2 of the ADF4216 family has been set to "1" (three-state the IF charge pump), and P7 is subsequently set to "1," then an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the IF power-down bit (P7).
Synchronous RF Power-Down
Programming a "1" to P16 of the ADF4216 family will initiate a power-down. If P10 of the ADF4216 family has been set to "0" (normal operation), a synchronous power-down is conducted. The device will automatically put the charge pump into three-state and then complete the power-down.
Asynchronous RF Power-Down
Control Bits C2 C1 0 0 1 1 0 1 0 1
Data Latch IF R Counter IF AB Counter (and Prescaler Select) RF R Counter RF AB Counter (and Prescaler Select)
If P10 of the ADF4216 families has been set to "1" (three-state the RF charge pump), and P16 is subsequently set to "1," an asynchronous power-down is conducted. The device will go into power-down on the rising edge of LE, which latches the "1" to the RF power-down bit (P16). Activation of either synchronous or asynchronous power-down forces the IF/RF loop's R and N dividers to their load state conditions and the IF/RF input section is debiased to a high impedance state. The REFIN oscillator circuit is only disabled if both the IF and RF power-downs are set. The input register and latches remain active and are capable of loading and latching data during all the power-down modes. The IF/RF section of the devices will return to normal powered up operation immediately upon LE latching a "0" to the appropriate power-down bit.
PROGRAM MODES
Table III and Table V show how to set up the Program Modes in the ADF4216 family. The following should be noted: 1. IF and RF Analog Lock Detect indicate when the PLL is in lock. When the loop is locked and either IF or RF Analog Lock Detect is selected, the MUXOUT pin will show a logic high with narrow low-going pulses. When the IF/RF Analog Lock Detect is chosen, the locked condition is indicated only when both IF and RF loops are locked.
REV. 0
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ADF4216/ADF4217/ADF4218
Table II. ADF4216 Family Latch Summary
IF REFERENCE COUNTER LATCH
THREE-STATE CPIF IF CP GAIN
NOT USED
IF PD POLARITY
IF LOCK DETECT
IF FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 P4
DB20 P3
DB19 P2
DB18 P5
DB17 P1
DB16
DB15 R14
DB14 R13
DB13 R12
DB12 R11
DB11 R10
DB10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
IF AB COUNTER LATCH
IF POWER-DOWN IF PRESCALER
NOT USED
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 P7
DB20 P6
DB19 B11
DB18 B10
DB17 B9
DB16 B8
DB15 B7
DB14 B6
DB13 B5
DB12 B4
DB11 B3
DB10 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (1)
RF REFERENCE COUNTER LATCH
THREE-STATE CPRF RF CP GAIN NOT USED RF PD POLARITY
RF LOCK DETECT
RE FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 P4
DB20 P3
DB19 P2
DB18 P5
DB17 P1
DB16
DB15 R14
DB14 R13
DB13 R12
DB12 R11
DB11 R10
DB10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (1)
DB0 C1 (0)
RF AB COUNTER LATCH
RF POWER-DOWN RF PRESCALER NOT USED
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 P7
DB20 P6
DB19 B11
DB18 B10
DB17 B9
DB16 B8
DB15 B7
DB14 B6
DB13 B5
DB12 B4
DB11 B3
DB10 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (1)
DB0 C1 (1)
-12-
REV. 0
ADF4216/ADF4217/ADF4218
Table III. IF Reference Counter Latch Map
THREE-STATE CPIF
IF CP GAIN
IF PD POLARITY
IF LOCK DETECT
IF FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 P4
DB20 P3
DB19 P2
DB18 P5
DB17 P1
DB16
DB15 R14
DB14 R13
DB13 R12
DB12 R11
DB11 R10
DB10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (0)
DB0 C1 (0)
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
R12 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383
P1 0 1
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
P5 0 1
ICP 1.25mA 4.375mA
P2 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
FROM RFR LATCH P12 P11 0 0 0 0 0 0 1 1 1 1 1 1 0 0 X X 1 1 X X 0 0 1 1
P4 0 0 1 1 0 0 0 0 1 1 1 1
P3 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT RF REFERENCE DIVIDER RF N DIVIDER FASTLOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT IF COUNTER RESET RF COUNTER RESET IF AND RF COUNTER RESET
REV. 0
-13-
ADF4216/ADF4217/ADF4218
Table IV. IF AB Counter Latch Map
IF PRESCALER IF POWER-DOWN
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 P7
DB20 P6
DB19 B11
DB18 B10
DB17 B9
DB16 B8
DB15 B7
DB14 B6
DB13 B5
DB12 B4
DB11 B3
DB10 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (0)
DB0 C1 (1)
A6 X X X X . . . X X
A5 X X X X . . . X X
A4 0 0 0 0 . . . 1 1
A3 0 0 0 0 . . . 1 1
A2 0 0 1 1 . . . 1 1
A1 0 1 0 1 . . . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3
14 15
B11 0 0 0 0 . . . 1 1 1 1
B10 0 0 0 0 . . . 1 1 1 1
B9 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 0 . . . 1 1 1 1
B2 0 0 1 1 . . . 0 0 1 1
B1 0 1 0 1 . . . 0 1 0 1
B COUNTER DIVIDER RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 2044 2045 2046 2047
P6 0 1
IF PRESCALER 8/9 16/17
P7 0 1
IF SECTION NORMAL OPERATION POWER-DOWN N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. TO ENSURE CONTINUOUSLY ADJACENT VALUES OF N, NMIN IS (P2 - P).
-14-
REV. 0
ADF4216/ADF4217/ADF4218
Table V. RF Reference Counter Latch Map
THREE-STATE CPRF
RF CP GAIN
RF PD POLARITY
RF LOCK DETECT
RF FO
14-BIT REFERENCE COUNTER, R
CONTROL BITS
DB21 P12
DB20 P11
DB19 P10
DB18 P13
DB17 P9
DB16
DB15 R14
DB14 R13
DB13 R12
DB12 R11
DB11 R10
DB10 R9
DB9 R8
DB8 R7
DB7 R6
DB6 R5
DB5 R4
DB4 R3
DB3 R2
DB2 R1
DB1 C2 (1)
DB0 C1 (0)
R14 0 0 0 0 . . . 1 1 1 1
R13 0 0 0 0 . . . 1 1 1 1
R12 0 0 0 0 . . . 1 1 1 1
.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
R3 0 0 0 1 . . . 1 1 1 1
R2 0 1 1 0 . . . 0 0 1 1
R1 1 0 1 0 . . . 0 1 0 1
DIVIDE RATIO 1 2 3 4 . . . 16380 16381 16382 16383
P9 0 1
PHASE DETECTOR POLARITY NEGATIVE POSITIVE
P13 0 1
ICP 1.25mA 4.375mA
P10 0 1
CHARGE PUMP OUTPUT NORMAL THREE-STATE
P12 0 0 0 0 0 0 1 1 1 1 1 1
P11 0 0 X X 1 1 X X 0 0 1 1
FROM IFR LATCH P4 P3 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1
MUXOUT LOGIC LOW STATE IF ANALOG LOCK DETECT IF REFERENCE DIVIDER OUTPUT IF N DIVIDER OUTPUT RF ANALOG LOCK DETECT RF/IF ANALOG LOCK DETECT RF REFERENCE DIVIDER RF N DIVIDER FASTLOCK OUTPUT SWITCH ON AND CONNECTED TO MUXOUT IF COUNTER RESET RF COUNTER RESET IF AND RF COUNTER RESET
REV. 0
-15-
ADF4216/ADF4217/ADF4218
Table VI. RF AB Counter Latch Map
RF POWER-DOWN
RF PRESCALER
11-BIT B COUNTER
6-BIT A COUNTER
CONTROL BITS
DB21 P16
DB20 P14
DB19 B11
DB18 B10
DB17 B9
DB16 B8
DB15 B7
DB14 B6
DB13 B5
DB12 B4
DB11 B3
DB10 B2
DB9 B1
DB8
DB7 A6
DB6 A5
DB5 A4
DB4 A3
DB3 A2
DB2 A1
DB1 C2 (1)
DB0 C1 (1)
A6 X X X X . . . X X
A5 X X X X . . . X X
A4 0 0 0 0 . . . 1 1
A3 0 0 0 0 . . . 1 1
A2 0 0 1 1 . . . 1 1
A1 0 1 0 1 . . . 0 1
A COUNTER DIVIDE RATIO 0 1 2 3
14 15
B11 0 0 0 0 . . . 1 1 1 1
B10 0 0 0 0 . . . 1 1 1 1
B9 0 0 0 0 . . . 1 1 1 1 .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........
B3 0 0 0 0 . . . 1 1 1 1
B2 0 0 1 1 . . . 0 0 1 1
B1 0 1 0 1 . . . 0 1 0 1
B COUNTER DIVIDE RATIO NOT ALLOWED NOT ALLOWED NOT ALLOWED 3 . . . 2044 2045 2046 2047
P14 0 1
RF PRESCALER 64/65 32/33
P16 0 1
RF SECTION NORMAL OPERATION POWER-DOWN N = BP + A, P IS PRESCALER VALUE SET BY P6. B MUST BE GREATER THAN OR EQUAL TO A. FOR ENSURE CONTINUOUSLY ADJACENT VALUES OF N, NMIN IS (P2 - P).
-16-
REV. 0
ADF4216/ADF4217/ADF4218
IF SECTION Programmable IF Reference (R) Counter
If control bits C2, C1 are 0, 0 then the data is transferred from the input shift register to the 14 Bit IF R counter. Table III shows the input shift register data format for the IF R counter and the divide ratios possible.
IF Phase Detector Polarity
programmable counter (B Counter). Table VI shows the input register data format for programming the RF N counter and the divide ratios possible.
RF Prescaler Value
P14 in the RF AB Counter Latch sets the RF prescaler value. Either 32/33 or 64/65 is available. See Table VI.
RF Power-Down
P1 sets the IF Phase Detector Polarity. When the IF VCO characteristics are positive, this should be set to "1." When they are negative, it should be set to "0." See Table III.
IF Charge Pump Three-State
Table IV and Table VI show the power-down bits in the ADF4216 family. See Power-Down section for functional description.
RF Fastlock
P2 puts the IF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table III.
IF Charge Pump Currents
P5 sets the IF Charge Pump current. With P5 set to "0," ICP is 1.25 mA. With P5 set to "1," ICP is 4.375 mA. See Table III.
Programmable IF AB Counter
If control bits C2, C1 are 0, 1, the data in the input register is used to program the IF AB counter. The AB counter consists of a 6-bit swallow counter (A counter) and 11-bit programmable counter (B counter). Table IV shows the input register data format for programming the IF AB counter and the divide ratios possible.
IF Prescaler Value
The RF CP Gain bit (P17) of the RF N register in the ADF4210 family is the Fastlock Enable Bit. Only when this is "1" is IF Fastlock enabled. When Fastlock is enabled, the RF CP current is set to its maximum value. Also an extra loop filter damping resistor to ground is switched in using the FLO pin, thus compensating for the change in loop characteristics while in Fastlock. Since the RF CP Gain bit is contained in the RF N Counter, only one write is needed both to program a new output frequency and to initiate Fastlock. To come out of Fastlock, the RF CP Gain bit on the RF N register must be set to "0." See Table VI.
APPLICATIONS SECTION Local Oscillator for GSM Handset Receiver
P6 in the IF AB Counter Latch sets the IF prescaler value. Either 8/9 or 16/17 is available. See Table IV.
IF Power-Down
Figure 7 shows the ADF4216 being used in a classic superheterodyne receiver to provide the required LOs (Local Oscillators). In this circuit, the reference input signal is applied to the circuit at REFIN and is being generated by a 13 MHz TCXO (Temperature Controlled Crystal Oscillator). In order to have a channel spacing of 200 kHz (the GSM standard), the reference input must be divided by 65, using the on-chip reference counter. The RF output frequency range is 1050 MHz to 1085 MHz. Loop filter component values are chosen so that the loop bandwidth is 20 kHz. The synthesizer is set up for a charge pump current of 4.375 mA and the VCO sensitivity is 15.6 MHz/V. The IF output is fixed at 125 MHz. The IF loop bandwidth is chosen to be 20 kHz with a channel spacing of 200 kHz. Loop filter component values are chosen accordingly.
Local Oscillator for WCDMA Receiver
Table III and Table V show the power-down bits in the ADF4216 family. See Power-Down section for functional description.
RF SECTION Programmable RF Reference (R) Counter
If control bits C2, C1 are 1, 0, the data is transferred from the input shift register to the 14-bit RFR counter. Table V shows the input shift register data format for the RFR counter and the divide ratios possible.
RF Phase Detector Polarity
P9 sets the IF Phase Detector Polarity. When the RF VCO characteristics are positive this should be set to "1." When they are negative it should be set to "0." See Table V.
RF Charge Pump Three-State
Figure 8 shows the ADF4217 being used to generate the local oscillator frequencies for a Wideband CDMA (WCDMA) system. The RF output range needed is 1720 MHz to 1780 MHz. The VCO190-1750T will accomplish this. Channel spacing is 200 kHz with a 20 kHz loop bandwidth. VCO sensitivity is 32 MHz/V. Charge pump current of 4.375 mA is used and the desired phase margin for the loop is 45. The IF output is fixed at 200 MHz. The VCO190-200T is used. It has a sensitivity of 11.5 MHz/V. Channel spacing and loop bandwidth is chosen to be the same as the RF side.
P10 puts the RF charge pump into three-state mode when programmed to a "1." It should be set to "0" for normal operation. See Table V.
RF Program Modes
Table III and Table V show how to set up the Program Modes in the ADF4216 family.
RF Charge Pump Currents
P13 sets the RF Charge Pump current. With P13 set to "0," ICP is 1.25 mA. With P5 set to "1," ICP is 4.375 mA. See Table V.
Programmable RF AB Counter
If control bits C2, C1 are 1, 1, the data in the input register is used to program the RF N (AB) counter. The AB counter consists of a 6-bit swallow counter (A Counter) and an 11-bit
REV. 0
-17-
ADF4216/ADF4217/ADF4218
IFOUT VP 100pF 18 18 100pF VCC VCO190-125T 18 3.9nF 3.3k 620pF 9k 400pF VP2 CPIF VDD2 VDD1 VP1 CPRF 620pF 5.8k 620pF 3.3k VCC VCO190-1068U 18 6nF 100pF 18 VDD VP 100pF 18 RFOUT
ADF4216
MUXOUT LOCK DETECT
1nF IFIN 51
DGNDRF AGNDRF DGNDIF AGNDIF
100pF RFIN 51 CLK DATA LE
VDD
REFIN
13MHz TCXO
DECOUPLING CAPACITORS (22 F/10pF) ON VDD1, VP, OF THE ADF4216, THE TCXO, AND ON VCC OF THE VCOs, HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 7. GSM Handset Receiver Local Oscillator Using the ADF4216
SPI-COMPATIBLE SERIAL BUS
IFOUT VP VDD VP
RFOUT
100pF 18 18 100pF VCC VCO190-200T 18 24nF 3.3k 450pF 1.5k 2.4nF
100pF 18
VP2 CPIF
VDD2 VDD1
VP1 CPRF 760pF 4.7k
3.3k 690pF
VCC VCO190-1750T
100pF 18
18 7.5nF
ADF4217
MUXOUT LOCK DETECT
1nF IFIN 51
DGNDRF AGNDRF DGNDIF AGNDIF
100pF RFIN 51 CLK DATA LE
VDD
REFIN
10MHz TCXO
DECOUPLING CAPACITORS (22 F/10pF) ON VDD1, VP, OF THE ADF4217, THE TCXO, AND ON VCC OF THE VCOs, HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 8. Local Oscillator for WCDMA Receiver Using the ADF4217
-18-
SPI-COMPATIBLE SERIAL BUS
REV. 0
ADF4216/ADF4217/ADF4218
INTERFACING ADSP-2181 Interface
The ADF4216/ADF4217/ADF4218 family has a simple SPIcompatible serial interface for writing to the device. SCLK, SDATA, and LE (Latch Enable) control the data transfer. When LE goes high, the 22 bits that have been clocked into the input register on each rising edge of SCLK will be transferred to the appropriate latch. See Figure 1 for the Timing Diagram and Table I for the Latch Truth Table. The maximum allowable serial clock rate is 20 MHz. This means that the maximum update rate possible for the device is 909 kHz or one update every 1.1 ms. This is certainly more than adequate for systems that will have typical lock times in hundreds of microseconds.
ADuC812 Interface
Figure 10 shows the interface between the ADF421x family and the ADSP-21xx Digital Signal Processor. As previously noted, the ADF421x family needs a 22-bit serial word for each latch write. The easiest way to accomplish this using the ADSP-21xx family is to use the Autobuffered Transmit Mode of operation with Alternate Framing. This provides a means for transmitting an entire block of serial data before an interrupt is generated. Set up the word length for eight bits and use three memory locations for each 22-bit word. To program each 22-bit latch, store the three 8-bit bytes, enable the Autobuffered mode and then write to the transmit register of the DSP. This last operation initiates the autobuffer transfer.
Figure 9 shows the interface between the ADF421x family and the ADuC812 microconverter. Since the ADuC812 is based on an 8051 core, this interface can be used with any 8051-based microcontroller. The microconverter is set up for SPI Master Mode with CPHA = 0. To initiate the operation, the I/O port driving LE is brought low. Each latch of the ADF421x family needs a 22-bit word. This is accomplished by writing three 8-bit bytes from the microconverter to the device. When the third byte has been written, the LE input should be brought high to complete the transfer. On first applying power to the ADF421x family, it requires four writes (one each to the R counter latch and the AB counter latch for both RF1 and RF2 side) for the output to become active. When operating in the mode described, the maximum SCLOCK rate of the ADuC812 is 4 MHz. This means that the maximum rate at which the output frequency can be changed will be about 180 kHz.
SCLK DT
SCLK SDATA LE
ADSP-21xx
TFS
ADF4216/ ADF4217/ ADF4218
I/O FLAG
MUXOUT (LOCK DETECT)
Figure 10. ADSP-21xx to ADF421x Family Interface
SCLOCK MOSI
SCLK SDATA LE
ADuC812
I/O PORTS
ADF4216/ ADF4217/ ADF4218
MUXOUT (LOCK DETECT)
Figure 9. ADuC812 to ADF421x Family Interface
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ADF4216/ADF4217/ADF4218
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.260 (6.60) 0.252 (6.40)
20
11
0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25)
1 10
PIN 1 0.006 (0.15) 0.002 (0.05) 0.0433 (1.10) MAX
SEATING PLANE
0.0256 (0.65) 0.0118 (0.30) BSC 0.0075 (0.19)
0.0079 (0.20) 0.0035 (0.090)
8 0
0.028 (0.70) 0.020 (0.50)
-20-
REV. 0
PRINTED IN U.S.A.
C01028-2.5-10/00 (rev. 0)
Thin Shrink Small Outline Package (TSSOP) (RU-20)

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